I can't quite understand how R3 could be able to accomodate 64k to R2 and 1.54mbps to R1 from a single 1.544mbps interface? Wouldn't a CIR of 1540000 on interface s 1/0 dlci 301 choke out the 64k on int s 0/1 dlci 302 to R2?
many thanks -
LG
r/
Tammy
Had the same issue. Before checking SG, I used 1472 with corresponding bc/be with 125ms.
It was discussed as well in the archives:
http://ieoc.com/forums/t/1765.aspx
Regards,
Smokey